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Senior Design Verification Engineer | Engineer in Engineering Job at Microsoft in Mountain View CA1

This listing was posted on ITJobsWeb.

Senior Design Verification Engineer

Location:
Mountain View, CA
Description:

Microsoft is a highly innovative company that collaborates across disciplines to produce cutting-edge technology that changes our world. Microsoft's Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality.We are looking for a Senior Design Verification Engineer to work on leading-edge Intellectual Property (IP) development as part of the Semi-Custom and Central Intellectual Property Silicon (SCIPS) team. Applicants should be interested in working in this cutting-edge technical environment.Microsoft's mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond. Qualifications: Required/Minimum Qualifications: 7+ years of related technical engineering experience OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field. 7+ years of experience in design verification with full verification cycle on complex System On Chip (SOC) IPs and/or systems. 5+ years experience with verification principles, testplan development, testbench creation, stimulus generation, Universal Verification Methodology (UVM) and coverage, debugging designs as well as creating simulation environments, with a proven track record of full verification cycle on complex SoC IPs and/or systems. 4+ years of C++ development experience. Other Requirements: Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. Preferred/Additional Qualifications: Knowledge of verification principles, testbenches, stimulus generation, UVM, and coverage. Experience in creating simulation environments, developing tests, and debugging designs. Understanding of chip and/or computer architecture. Experience wiith scripting language such as Python, Ruby. Experience with System Verilog and UVM Hardware security IP and SOC level verification Firmware development experience, with secure and non-secure boot flow Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $112,000 - $218,400 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $145,800 - $238,600 per year.Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-payMicrosoft will accept applications for the role until May 21, 2024.Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.#azurehwjobs #HIFE Responsibilities: Establish yourself as an integral member of a pre-silicon verification and post-silicon validation team for the development of customIntellectual Property (IP)components. Define pre-Silicon verification (simulation/emulation/formal proofs/field-programmable gate array (FPGA) and post-Silicon validation strategies. Work with a team to write, execute, enhance, and debug constrained random stimulus, scoreboards and checkers, and assertions to verify design correctness. DevelopUniversal Verification Methodology(UVM)components to interface between test code and verification simulation environments. Define and implement functional coverage and drive coverage closure. Collaborate across verification teams on vertical and horizontal reuse of components. Interact with Architecture, Design, Firmware/Software, Product Engineering, Program Management and third party vendor teams to ensure pre-and-post-Silicon testing is comprehensive. Writescripts for verification and validation infrastructure. Apply Agile development methodologies including code reviews, sprint planning, and feature deployment. Providetechnical leadership through mentorship and teamwork. Embody our Culture and Values Requisition #: 1700878pca3lyuhf
Company:
Microsoft
Posted:
May 6 on ITJobsWeb
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